1. Technical Field
The present invention relates generally to a data transmission system and, more particularly, to a data recovery circuit and method for minimizing errors due to clock skew.
2. Description of Related Art
In general, in a data transmission system for transmitting predetermined data, the use of parallel transmission channels is a popular method for digitally interfacing systems. However, problems may occur with this method of using the parallel transmission channels if the number of data transmission channels increases. Consequently, a serial transmission method is gradually replacing the parallel transmission method.
With the serial transmission method, the number of channels used for transmitting data is less than the number of channels used for transmitting data using the parallel transmission method. However, in most cases, when data is transmitted using serial transmission channels, a high speed serial signal must be converted to a parallel data format at a receiving end. When serial data is converted to the parallel data format, it may be difficult to recover data due to clock skew at the receiving end.
Using conventional technology, in order to solve such a problem, a bit section of a received signal is sampled many times and a data level is determined by detecting the generation frequency of the sampled result. With this method of determining data by detecting the generation frequency of data, however, errors may occur in a portion at which the level of data is converted due to the accumulation of clock skew. For example, in a level transition section, in which the level of data is transited from a logic “high” level to a logic “low” level or from the logic “low” level to a logic “high” level, there is every possibility that the data determined by the generation frequency thereof is not real data but erroneous data.